Verification of Safe Operating Area (SOA) Constraints in Analog Circuits

Konferenz: Zuverlässigkeit und Entwurf - 2. GMM/GI/ITG-Fachtagung
29.09.2008 - 01.10.2008 in Ingolstadt, Germany

Tagungsband: Zuverlässigkeit und Entwurf

Seiten: 2Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Sobe, Udo; Rooch, Karl-Heinz; Mörtl, Dietmar; Graupner, Achim (ZMD AG, Grenzstraße, 01109 Dresden)
Lerch, André (X-FAB Semiconductor Foundries AG, Haarbergstraße, 99097 Erfurt)
Pronath, Michael (MunEDA GmbH, Stefan-George-Ring, 81929 München)

Simulation of degradation effects of aging (e.g. negative bias temperature instability (NBTI), hot carrier stress (HC)) have been a topic of research for nearly two decades. These reliability models and corresponding simulation techniques are not yet widely available in current process development kits (PDK) and design flows. In general, process documentation contains information about safe operating areas (SOA) such as maximum current and voltage stress of the devices. How this information can be used with current tools for design, verification and optimization today is presented in this paper.