UV NIL template making and imprint evaluation

Konferenz: EMLC 2009 - 25th European Mask and Lithography Conference
12.01.2009 - 15.01.2009 in Dresden, Germany

Tagungsband: EMLC 2009

Seiten: 7Sprache: EnglischTyp: PDF

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Sasaki, Shiho; Hiraka, Takaaki; Mizuochi, Jun; Sakai, Yuko; Yusa, Satoshi; Morikawa, Yasutaka; Mohri, Hiroshi; Hayashi, Naoya (Electronic Device Laboratory, Dai Nippon Printing Co., Ltd., 2-2-1 Fukuoka, Fujimino-shi, Saitama, 356-8507 Japan)

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers. Usually such templates needed just a small field (several hundred microns square or so) Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D purpose but eventually as a potential candidate for production, and instead of a small field, a full chip field mask is required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to generate the pattern and have a fatally low throughput if we need full chip writing. In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we achieved resolution down to hp28nm, and initial promising results of hp22nm (partial resolution) for line and spaces, and hp26nm for dense holes were observed.