Design Verification for sub 70 nm DRAM nodes via Metal Fix using E-Beam Direct Write

Konferenz: EMLC 2009 - 25th European Mask and Lithography Conference
12.01.2009 - 15.01.2009 in Dresden, Germany

Tagungsband: EMLC 2009

Seiten: 5Sprache: EnglischTyp: PDF

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Keil, K.; Jaschinsky, P. (Fraunhofer CNT)
Hohle, C.; Choi, K.-H.; Tesauro, M.; Thrum, F.; Zimmermann, R.; Kretz, J. (Qimonda Dresden GmbH & Co. OHG, Koenigsbruecker Straße 180, D-01099 Dresden, Germany)
Schneider, R. (Qimonda AG, Am Campeon 1-12, D-85579 Neubiberg, Germany)

Because of mask cost reduction, electron beam direct write (EBDW) is implemented for special applications such as rapid prototyping or small volume production in semiconductor industry. One of the most promising applications for EBDW is design verification by means of metal fix. Due to write time constrains, Mix & Match solutions have to be developed at smaller nodes. This study reports on several Mix & Match processes for the integration of E-Beam lithography into the optical litho process flow of Qimonda’s 70 nm and 58 nm DRAM nodes. Different metal layers have been patterned in part with DUV litho followed by E-Beam litho using a 50 kV Vistec SB3050 shaped electron beam direct writer. All hardmask patterns were then simultaneously transferred into the DRAM stack. After full chip processing a yield study comprising electrical device characterization and defect investigation was performed. We show detailed results including CD and OVL as well as improvements of the alignment mark recognition. The yield of the E-Beam processed chips was found to be within the range of wafer-to-wafer fluctuation of the POR hardware. We also report on metal fix by electrical cutting of selected diodes in large chip scales which usually cannot be accessed with FIB methods. In summary, we show the capability of EBDW for quick and flexible design verification.