Hauger, Simon; Mutter, Arthur; Kirstädter, Andreas; Feller, Frank; Scharf, Joachim (Institute of Communication Networks and Computer Engineering (IKR), Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany)
Wild, Thomas; Karras, Kimon; Ohlendorf, Rainer (Institute for Integrated Systems (LIS), Technische Universität München (TUM), Arcisstraße 21, 80290 Munich, Germany)
The continuous growth of traffic volumes steadily raises the throughput requirements on the network infrastructure. Additionally, a transformation of the classical TDM-based backbone networks to packet networks with Carrier Ethernet as the target technology occurs. The standardization process of 100 Gbps Ethernet is under way. This not only poses big challenges to transmission but also to packet processing technologies. However, recent announcements from network processing unit (NPU) vendors promise that packet processing at 100 Gbps is feasible. The big question for system manufacturers now is, whether this trend will continue and finally lead to 1 Tbps packet switching, or whether there are technological roadblocks that inhibit this development path. In this paper, we address this question and identify packet processing performance, packet buffer throughput, chip-to-chip interface speed, and power dissipation as the most critical factors. We discuss their limiting factors as well as architectural and technological trends that can further increase their performance. Based on these investigations and extrapolating anticipated technological advances we expect that 1 Tbps packet processing and switching could be introduced in the network within several years. Since this, however, not only depends on technological but also on economical factors, we show how slight modifications of the network architecture and protocols could alleviate some implementation complexities and thus reduce the overall cost.