Learning Optimal Synthesis of Voltage Regulator Circuits through Comparative Study in PSPICE

Konferenz: ISTET 2009 - VXV International Symposium on Theoretical Engineering
22.06.2009 - 24.06.2009 in Lübeck, Germany

Tagungsband: ISTET 2009

Seiten: 5Sprache: EnglischTyp: PDF

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Marinova, Galia; Dimitrov, Dimitar (Technical University – Sofia)

The paper presents a Learning Environment for Optimal Synthesis of Voltage Regulator Circuits (LEOS-VRC) using PSPICE simulator. LEOS-VRC can help teaching and self education in design of voltage regulator circuits. It’s suitable for students in electronics, electrotechniques, telecommunications and computer-science engineering as well as doctoral students and designers of power supply circuits.