Learning Environment for Design and Verification of Communication Circuits Realized on FPGA

Konferenz: ISTET 2009 - VXV International Symposium on Theoretical Engineering
22.06.2009 - 24.06.2009 in Lübeck, Germany

Tagungsband: ISTET 2009

Seiten: 3Sprache: EnglischTyp: PDF

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Marinova, Galia (Technical University – Sofia)

The paper presents a Learning Environment for design and verification of communication circuits realized on FPGA, which is developed and applied in the laboratory for Computer-aided design in the Telecommunications faculty in Technical University (TU) – Sofia. IP blocks of digital signal processing functions and communication systems like modems and cryptoprocessors can be designed and tested in the environment.