Metric-Driven Validation and Verification of Software for Embedded Systems
Konferenz: Zuverlässigkeit und Entwurf - 3. GMM/GI/ITG-Fachtagung
21.09.2009 - 23.09.2009 in Stuttgart, Germany
Tagungsband: Zuverlässigkeit und Entwurf
Seiten: 2Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Winterholer, Markus (Cadence Design Systems GmbH, Feldkirchen, Germany)
Today software is mostly validated and verified using directed testing. However this approach risks being very time consuming, lacks sufficient automation and reuse potential, and causes high maintenance effort. It also ignores high value verification and validation aspects within the embedded system that may not have been thought of, either because they were not anticipated or because there was simply no time to write such tests, which could lead to costly missed bugs. This presentation introduces a functional verification and validation strategy for embedded software that can be applied very early in the design process of an embedded system. It can be used continuously during all refinement steps, minimizing the required manual adoptions.