Increasing Test Quality and Device Reliability by Test Simulation
Konferenz: Zuverlässigkeit und Entwurf - 3. GMM/GI/ITG-Fachtagung
21.09.2009 - 23.09.2009 in Stuttgart, Germany
Tagungsband: Zuverlässigkeit und Entwurf
Seiten: 7Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Lu, Ping; Glaser, Daniel; Uygur, Guerkan; Weichslgartner, Susanne; Helmreich, Klaus (Chair of Reliable Circuits and Systems, Friedrich-Alexander-University Erlangen-Nuremberg, Paul-Gordan-Str. 5, 91052 Erlangen, Germany)
Lechner, Armin (Konrad-Technologie GmbH, Fritz-Reichele-Ring. 5, 78315 Radolfzell, Germany)
A novel virtual platform is presented, providing CAD/CAT support for efficient test development and attempting to bridge the gap between design and test. The platform, which models and simulates the entire test environment, provides methodologies, model libraries and tool sets to enable design, debug and verification of all test relevant processes including fault analysis, test algorithm, load board and test program development concurrently with IC design and fabrication phase and later smoothly apply the results to various test systems. The introduced approach leads to higher test quality, more decisive tests and thus contributes to higher device reliability in application. One major idea of our work is adopting the open standards approach to guarantee interoperability. In addition, modeling methodologies for virtual tester and virtual silicon are proposed to further enhance interoperability between virtual and real test. To give an insight on how such environment seamlessly integrates into the test development flow, an ADC test which is performed both on the virtual platform and the real tester is described. The simulation environment is built using SystemC/AMS libraries.