System based optimization of the chip size and the thermal path for Si and SiC semiconductors
Konferenz: CIPS 2010 - 6th International Conference on Integrated Power Electronics Systems
16.03.2010 - 18.03.2010 in Nuremberg, Germany
Tagungsband: CIPS 2010
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Köneke, Thies; Merkert, Arvid; Mertens, Axel (Institute for Drive Systems and Power Electronics, Leibniz University Hannover, Germany)
The appearance of wide band gap power transistors raises the question, if the known technical advantages of Wide-Band-Gap-semiconductors also yield economical benefits. Therefore the technical advantages must be quantified in a first step. Several figures of merit (FOMs) were derived in the past in order to compare the semiconductor materials in power semiconductor applications. Most popular is the so called unipolar limit, which leads to a large advantage of WBG-materials compared to Si. But this is misleading, since the overall performance of WBG-devices is significantly lower. Especially, the comparison between unipolar and bipolar power semiconductor devices could not be expressed in a FOM so far. This paper examines the switching behaviour of a SiC-JFET and introduces a practical approach to optimize the chip size of bipolar and unipolar power transistors. Two optimization criteria are presented, which lead to the system depending "Minimum-Loss" and "Minimum-Cost" device performance factors MLDPF and MCDPF. These factors are calculated for a SiC-JFET and a Si-IGBT. The comparison of these results with commonly used FOMs, which are review at the beginning, shows, how far the theoretical advantages of SiC can be applied to real system designs.