Online Transient Error Detection and Recovery in Re-order Buffers of Superscalar Processors
Konferenz: Zuverlässigkeit und Entwurf - 4. GMM/GI/ITG-Fachtagung
13.09.2010 - 15.09.2010 in Wildbad Kreuth, Germany
Tagungsband: Zuverlässigkeit und Entwurf
Seiten: 8Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Shazli, Syed (Northeastern University, Boston, MA, USA)
Tahoori, Mehdi (Karlsruhe Institute of Technology, Karlsruhe, Germany)
Transient errors are a major reliability barrier for modern processors. The vulnerability of processor cores to such errors grows exponentially with technology scaling. To meet reliability constraints in a cost-effective way, it is critical to localize the effects of these errors and prevent them from propagating to other parts of the system. In this work, we look at state-of-the-art superscalar processors that use deep pipelines, speculative execution and can issue multiple instructions per cycle. We present a methodology to provide low-cost detection and recovery of transient errors occurring in Reorder buffers used in these processors. The technique has been implemented on a cycle accurate, architectural simulator. Using the approach, we are able to detect and recover from all single bit upsets with less than 5% increase in CPI and 3% area overhead for ROB.