A flexible hardware architecture for real-time airborne Wavenumber Domain SAR processing

Konferenz: EUSAR 2012 - 9th European Conference on Synthetic Aperture Radar
23.04.2012 - 26.04.2012 in Nuremberg, Germany

Tagungsband: EUSAR 2012

Seiten: 4Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (Institute of Microelectronic Systems, Leibniz University Hannover, Germany)

This paper presents the design of a compact real-time SAR hardware architecture for small unmanned aerial vehicles (UAVs). The architecture is flexible for a variety of SAR algorithms whereby the focus of this paper is on the wavenumber domain (ω-k) algorithm. Characteristics of the RISC/FPGA based hardware architecture are real-time processing for sensor data rates of 300 Mbit/s with image dimensions of 8k x 4k pixel, implemented on a 233 x 160 mm printed circuit board with a total power dissipation below 15 W.