Design and Implementation of Fast SAR Echo Simulation Based on FPGA

Inhalt:
Synthetic Aperture Radar (SAR) echo simulation needs massive calculation and takes much time. In order to simulate SAR echo quickly, this paper presents a method of fast SAR echo simulation which is based on an improved equivalent scatterer echo algorithm, A hardware-in-Ioop SAR echo simulator with flexible configuration is designed. FPGA-based parallel realization is optimized. The application result shows that the SAR echo simulator can generate high-accuracy echo data and the speed of echo simulation is increased significantly.