Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure

Konferenz: CIPS 2012 - 7th International Conference on Integrated Power Electronics Systems
06.03.2012 - 08.03.2012 in Nuremberg, Germany

Tagungsband: CIPS 2012

Seiten: 6Sprache: EnglischTyp: PDF

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Liang, Zhenxian; Ning, Puqi; Wang, Fred; Marlino, Laura (Oak Ridge National Laboratory, Oak Ridge, TN, USA)

A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. The power switches in a popular phase leg electrical topology are orientated in a face up/face down configuration. Large bonding areas between dies and substrates combined with a compact busbar interface allow this packaging technology to offer dramatic improvements in electrical conversion efficiency and electromagnetic interference containment.