Design of CMOS Gated Analog Readout Circuits for SPAD Pixel Arrays
Konferenz: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
12.06.2012-15.06.2012 in Aachen, Germany
Tagungsband: PRIME 2012
Seiten: 4Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Panina, Ekaterina; Dalla Betta, Gian-Franco (NMS Lab., DISI, University of Trento, Trento, Italy)
Pancheri, Lucio; Stoppa, David (Smart Optical Sensors and Interfaces (SOI), Fondazione Bruno Kessler (FBK), Trento, Italy)
Advanced microscopy applications such as Fluorescence Lifetime Imaging Microscopy (FLIM) require detectors possessing high detection efficiency of incident photons and high timing resolution at the same time. One of the emerging technologies in this field is based on Single-Photon Avalanche Diodes (SPADs) which can easily be integrated into arrays in conventional CMOS technologies, providing picosecond timing resolution at a low fabrication cost. The feasibility of in-pixel analog processing circuits to replace area-consuming digital readout circuits has been recently demonstrated. Without sacrificing counting accuracy, analog circuits contain a much lower number of transistors, making the pixel design compact. In this paper we present an analysis of two different analog readout circuits for compact SPAD pixels. The proposed analog counters offer sub-nanosecond gating capabilities and are therefore suitable for FLIM applications. Keywords: SPAD, CMOS, image sensor, FLIM.