Multiplexer Based Design for Ternary Logic Circuits

Konferenz: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
12.06.2012-15.06.2012 in Aachen, Germany

Tagungsband: PRIME 2012

Seiten: 4Sprache: EnglischTyp: PDF

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Vudadha, Chetan; Sreehari, V.; Srinivas, M. B. (Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, 50078, India)

Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a methodology for the design of ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. The proposed methodology is multiplexer based design. First a design of ternary multiplexer is presented. Then the proposed methodology for design of ternary logic circuits is presented. The proposed design methodology is used to implement 1-bit comparator and half adder circuits using SPICE. The proposed implementations are compared with the existing designs for parameters like delay, power etc. Simulation results indicate that the proposed multiplexer based 1-bit half adder design results in 27% delay reduction and 23% power delay product reduction when compared to the existing design. Keywords - CNFET; Ternary logic; Ternary Multiplexer