A 9 bit 34 MS/s SAR Analog-to-Digital Converter in 130 nm SiGe BiCMOS
Konferenz: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
12.06.2012-15.06.2012 in Aachen, Germany
Tagungsband: PRIME 2012
Seiten: 4Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Digel, Johannes; Grözing, Markus; Berroth, Manfred (Institute of Electrical and Optical Communications Engineering, University of Stuttgart, Germany)
A 9 bit 34 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The successive approximation is realized with a switched-capacitor digitalto- analog converter (SC-DAC) which is very power efficient. The switching control and SAR are implemented with special flip-flops that have two delay inputs. The classical switching algorithm is extended to be capable of deriving one additional bit. The ADC is implemented in a 130 nm SiGe BiCMOS technology. The chip size is 2.1×0.7 mm2 while the ADC core only occupies 0.3×0.2 mm2. At a conversion rate of 22 MS/s the SNDR and SFDR are 49.3 dB and 59.8 dB with a low frequency input. For Nyquist frequency, SNDR and SFDR are 48.7 dB and 59.0 dB. The effective resolution bandwidth (ERBW) is 30 MHz. The ADC consumes 3.3 mW from a 1.3 V supply and has a FoM of 630 fJ/conv. step at 22 MS/s.