Design of a Low Noise Frequency-synthesizers for Digital Video Broadcasting-Handheld System

Konferenz: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
12.06.2012-15.06.2012 in Aachen, Germany

Tagungsband: PRIME 2012

Seiten: 4Sprache: EnglischTyp: PDF

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Haolei, Wang; Shun’an, Zhong; Hua, Dang; Xianli, Zhao (Information and Electronics Department, Beijing Institute of Technology, Beijing, 100081, P. R. China)

In this work, The design of PLL frequency synthesizer for the digital video broadcasting-handheld (DVB-H) is proposed. A system study of a zero-IF dual band DVB-H tuner is described. To meet the required noise figure specification, a 3- order ΣΔ| fractional-N PLL is adopted to cover UHF band and L band. At last, the design and implementation of key circuits in the PLL loop is presented. A wideband VCO can be employed which covers a range of frequency 1.5 to 1.8 GHz. The synthesizer which implemented in 0.18 um CMOS achieved a low phase noise with -126 dBc/Hz @ 1MHz frequency offset in simulation. Index Terms — Digital video broadcasting-handheld (DVB-H), dual modulus prescalers, phase-locked loops (PLLs), extended true single phase clock logic (ETSPC).