Scratch Reduction by using Nano-colloidal Ceria Slurry with Multiselectivity of SiO2/Si3N4/Poly-Si Films in STI-CMP
Konferenz: ICPT 2012 - International Conference on Planarization / CMP Technology
15.10.2012-17.10.2012 in Grenoble, France
Tagungsband: ICPT 2012
Seiten: 6Sprache: EnglischTyp: PDF
Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Autoren:
Kang, Hyun-Goo; Koh, Jeong-Deog; Han, Seung-Woo; Lee, Jin Won; Lee, Byoun-Gki; Pyi, Seung- Ho; Lee, Byung-Seok; Kim, Jin-Woong (Skhynix Semiconductor Inc., Bubal-eup, Icheon-si, Gyeonggi-do, Korea)
Reiss, Brian; Jeong, Jae-Deok; Nam, Chul-Woo; Jang, Ju-Yeon; Choi, Kyo-Se; Dysard, Jeffrey; Woodland, Daniel (Cabot Microelectronics Corp., USA)
Inhalt:
In this study, we have been developed the nano-colloidal ceria slurry and the polymer additive added to control the multi-removal selectivity of SiO2, Si3N4, and poly-Si films in STI-CMP. We obtained high selectivity between SiO2-to-poly-to-Si3N4 films about 100:1:30 and good scratch performance which was improved about 1 order compared to conventional calcined ceria slurry. The average number of scratches for conventional calcined ceria slurry (240 counts / wafer) was a little larger than that for new nano-colloidal ceria slurry (20 counts / wafer) in pattern wafer tests. In other words, we confirmed the polishing scratch defects on patterned wafer surface were significantly restrained, while maintaining the reasonable SiO2 removal rate and SiO2, Si3N4 and poly-Si removal selectivity. Keywords: Planarization, Chemical-mechanical Polishing, STI-CMP, Ceria slurry