A Self-Calibration High Speed Dual Slope ADC for SoC Sensor Applications

Konferenz: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
04.03.2013 - 06.03.2013 in Aachen, Deutschland

Tagungsband: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden

Seiten: 6Sprache: EnglischTyp: PDF

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Scholl, Markus; Zhang, Ye; Mohr, Bastian; Wunderlich, Ralf; Heinen, Stefan (Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany)

This paper presents an area-efficient high-accuracy Dual Slope ADC for SOC sensor applications based on a CTAT voltage generated by the base-emitter voltage of a bipolar transistor in a bandgap. The non-idealities in Dual Slope ADCs are discussed and analyzed in detail, including individual components as well as system topology. A high efficient calibration method is proposed to overcome the non-ideal issues, such as comparator offset voltage, propagation delay, OP offset voltage and finite gain. Both from calculation and transistor level simulation, the proposed ADC gains a higher resolution than a conventional structure. It is able to achieve more than 7 bit and 490 kHz sampling speed. The proposed Dual Slope ADC was designed and fabricated in a 65 nm CMOS process. The circuit area is 8900 µm2 consuming 0.9 mW power from a 1.2 V power supply.