A Self-Calibration High Speed Dual Slope ADC for SoC Sensor Applications

Inhalt:
This paper presents an area-efficient high-accuracy Dual Slope ADC for SOC sensor applications based on a CTAT voltage generated by the base-emitter voltage of a bipolar transistor in a bandgap. The non-idealities in Dual Slope ADCs are discussed and analyzed in detail, including individual components as well as system topology. A high efficient calibration method is proposed to overcome the non-ideal issues, such as comparator offset voltage, propagation delay, OP offset voltage and finite gain. Both from calculation and transistor level simulation, the proposed ADC gains a higher resolution than a conventional structure. It is able to achieve more than 7 bit and 490 kHz sampling speed. The proposed Dual Slope ADC was designed and fabricated in a 65 nm CMOS process. The circuit area is 8900 µm² consuming 0.9 mW power from a 1.2 V power supply.