Signal Integrity Trainings for Multi-clock Source-Synchronous Memory Systems

Konferenz: Zuverlässigkeit und Entwurf - 7. ITG/GI/GMM-Fachtagung
24.09.2013 - 26.09.2013 in Dresden, Deutschland

Tagungsband: Zuverlässigkeit und Entwurf

Seiten: 4Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Autoren:
Fang, Yuan; Jaiswal, Ashok; Hofmann, Klaus (TU Darmstadt, Merckstr. 25, Darmstadt, Germany)

Inhalt:
To ensure the signal integrity, different trainings are used in advanced high-speed multi-clock source-synchronous systems such as GDDR5 for the robust design. In this paper, a multi-clock synchronization training using a) unit-delay incrementer b) phase interpolator (PI)-based phase-locked loop (PLL) architectures are proposed. Experiments show that the proposed unit-delay architecture consumes only 0.89 mW power and 100 (µm)2 area in 65nm technology which is 16.8 times less power and 35 times less area than other works while power and area consumed in the PI-based PLL architecture depends upon the complexity of the PI itself. In addition, an adaptive equalization training is introduced for a GDDR5 memory system to compensate for inter-symbol interference (ISI) and/or cross talk in the data channels. For the low-power design, the equalizers are applied only in the memory controller utilizing the existing GDDR5 memory interface. This system architecture is verified by implementing the receiver equalizer training at the circuit level and the transmitter equalizer training using different algorithms: 1) LMS algorithm 2) pilot signal/peak detection in Matlab/Simulink. LMS algorithm improves the vertical and horizontal eye opening by more than 30% and 10%, respectively.