Symbolic Fault Modeling and Model Counting for the Identification of Critical Gates in Digital Circuits

Konferenz: ZuE 2015 - 8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf – Reliability by Design
21.09.2015 - 23.09.2015 in Siegen, Deutschland

Tagungsband: GMM-Fb. 83: ZuE 2015

Seiten: 8Sprache: EnglischTyp: PDF

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Bernardini, Alessandro; Schlichtmann, Ulf (TU München, Germany)

We describe a symbolic modeling for handling bit-flips and glitches in digital circuits. Using Model Counting we can compute the conditional error probability and we can efficiently order gates according to their criticality for selective hardening. We can handle sets of gates symbolically as a whole and using ROBDD or #SAT Algorithms we obtain an exact solution without repeatedly injecting errors. Multiple bit-flips can be handled as well. We can consider correlated input patterns. We show the performance of the symbolic modeling when processing set of gates instead of repeatedly considering a single gate, without losing detailed information.