Stochastic analysis of degradation and variations in CMOS-Transistors
Konferenz: ZuE 2015 - 8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf – Reliability by Design
21.09.2015 - 23.09.2015 in Siegen, Deutschland
Tagungsband: GMM-Fb. 83: ZuE 2015
Seiten: 8Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Hillebrand, Theodor; Hellwege, Nico; Heidmann, Nils; Paul, Steffen; Peters-Drolshagen, Dagmar (University of Bremen ITEM, Bremen, Germany)
Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a simulation environment that provides an inside into the internal dependencies between these two crucial effects. In this paper a predictive and technology independent model for considering process variations and degradation simultaenously is presented. The main idea refers to the calculation of transistor operating points with the influence of process variation. Subsequently these operating points are degraded through Hot Carrier Injection and Bias Temperature Instability. The probability density function for the change in the threshold voltage DeltaVth is extracted and is fitted over time. This analytical expression is used to provide a simple way to calculate an accurate estimation of a normalized DeltaVth.