Yield Analysation and Optimization Methods for Active CMOS Pixels
Konferenz: ZuE 2015 - 8. GMM/ITG/GI-Fachtagung Zuverlässigkeit und Entwurf – Reliability by Design
21.09.2015 - 23.09.2015 in Siegen, Deutschland
Tagungsband: GMM-Fb. 83: ZuE 2015
Seiten: 8Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Lindner, Claus; Soell, Christopher; Roeber, Juergen; Baenisch, Andreas; Weigel, Robert (Institute for Electronics Engineering, FAU Erlangen-Nuremberg, Germany)
This work explains how to simulate error sources in image sensors to analyze yield. Moreover, two circuitry-wise methods to reduce these interferences are proposed and their influences on yield and standard deviation caused by process variations and reset noise are analyzed. Thereby the biggest sources of interference within the pixel architectures are described. After comparing three different pixel architectures, their extracted layout is simulated and the results are compared. Especially the change of the yield and the standard deviation with and without the use of DS and CDS are analyzed. By applying the methods mentioned before the yield could be increased by up to 15.6 %.