Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency
Konferenz: CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems
08.03.2016 - 10.03.2016 in Nürnberg, Deutschland
Tagungsband: CIPS 2016
Seiten: 5Sprache: EnglischTyp: PDF
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Autoren:
Pillonnet, Gael (Université Grenoble Alpes, 38000 Grenoble, France & CEA, LETI, MINATEC Campus, 38054 Grenoble, France)
Jeanniot, Nicolas (Université Grenoble Alpes, 38000 Grenoble, France & CEA, LETI, MINATEC Campus, 38054 Grenoble, France & University of Lyon, CPE department, 69616, Villeurbanne, France)
Inhalt:
Integrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares the achievable efficiencies of the 2:1 switched capacitor DC-DC converter topology under the same constraints in 65, 130 and 350 nm bulk CMOS nodes and 28 nm in bulk and FDSOI technologies with various capacitor options.