A Miniaturized High Resolution SAR Processor Using FPGA
Konferenz: EUSAR 2016 - 11th European Conference on Synthetic Aperture Radar
06.06.2016 - 09.06.2016 in Hamburg, Germany
Tagungsband: EUSAR 2016
Seiten: 4Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Zhu, Daiyin; Zhang, Jindong; Mao, Xinhua; Zhang, Ying; Wang, Xudong; Li, Yong; Ding, Yong; Guo, Jiangzhe; Shi, Jianing (Key Laboratory of Radar Imaging and Microwave Photonics, Ministry of Education, College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, China)
Implementation of a miniaturized SAR processor using Virtex-7 FPGA is described in this paper. The polar format algorithm (PFA) is accelerated by utilizing the chirp scaling principle to avoid the two dimensional interpolation. Moreover, an efficient two dimensional autofocus scheme is applied as an effective complementarity to the low cost motion sensor. The FPGA design and resource utilization are investigated, and the accuracy of the processing results are compared with those obtained on a personal computer. The system is now able to process 8K by 8K complex-image in a single precision within 15 seconds when the FPGA work at 200MHZ clock.