Power-Down Schematic Synthesis for Analog/Mixed-Signal Circuits
Konferenz: ANALOG 2016 - 15. ITG/GMM-Fachtagung
12.09.2016 - 14.09.2016 in Bremen, Germany
Tagungsband: ITG-Fb. 266: Analog 2016
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Neuner, Maximilian; Zwerger, Michael; Graeb, Helmut (Institute for Electronic Design Automation, Technical University of Munich, Munich, Germany)
Power management features gained a lot of importance in modern chip design. For analog/mixed-signal circuits, complementary power-down circuitry is implemented which shuts down all of its bias currents if the circuit is not in use. Power-down circuitry can be automatically synthesized into the structure of a given circuit. The results of this method are not easily accessible by the circuit designer, because the power-down transistors are not visualized in the schematic of the circuit. In this work, a power-down schematic synthesis method is presented which automatically places the computed power-down transistors into the schematic. Thereby, the original schematic is changed as least as possible. The synthesized schematic can be directly displayed for further circuit development by schematic editors of commercial tools. Experimental results are presented for a Miller OpAmp and a folded cascode amplifier with bias circuitry.