Development of a low temperature SiC protection layer for post-CMOS MEMS fabrication utilizing vapour release technologies

Konferenz: Mikro-Nano-Integration - 6. GMM-Workshop
05.10.2016 - 06.10.2016 in Duisburg, Deutschland

Tagungsband: GMM-Fb. 86: Mikro-Nano-Integration

Seiten: 6Sprache: EnglischTyp: PDF

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Autoren:
Walk, Christian; Kuhl, Andreas; Goertz, Michael; Vogt, Holger (Fraunhofer Institute for Microelectronic Circuits and Systems, Finkenstr. 61, 47057 Duisburg, Germany)
Chen, Yizhou (Fraunhofer Institute for Microelectronic Circuits and Systems, Finkenstr. 61, 47057 Duisburg, Germany & Faculty of Electrical Engineering and Information Technology, Karlsruhe Univ. of Applied Sciences, Germany)
Vidovic, Nino (Fraunhofer Institute for Microelectronic Circuits and Systems, Finkenstr. 61, 47057 Duisburg, Germany & Department of Microsystems Engineering - IMTEK, Univ. of Freiburg, Germany)

Inhalt:
In post-CMOS processing a sufficient protection of the underlying CMOS structures, while applying sacrificial layer release technologies to realize free standing MEMS, is required. In this work, a low temperature Silicon Carbide (SiC) process at 300 °C by Inductively Coupled Plasma Chemical Vapour Deposition (ICPCVD) has been developed. It has been demonstrated, that SiC provides an excellent protection character in HF/H2O vapour mixtures. For proof of principle, perforated free-standing SiC-structures with a layer thickness of less than 200 nm and 80 mm in diameter have successfully been released in a vapour etch process.