Integration of wet-etched GaN nanowires for vertical power transistors

Konferenz: Mikro-Nano-Integration - 6. GMM-Workshop
05.10.2016 - 06.10.2016 in Duisburg, Deutschland

Tagungsband: GMM-Fb. 86: Mikro-Nano-Integration

Seiten: 4Sprache: EnglischTyp: PDF

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Autoren:
Yu, Feng; Wasisto, Hutomo Suryo; Waag, Andreas (Institute of Semiconductor Technology (IHT), TU Braunschweig, Braunschweig, Germany & Laboratory for Emerging Nanometrology (LENA), TU Braunschweig, Braunschweig, Germany)
Yao, Shengbo (Institute of Semiconductor Technology (IHT), TU Braunschweig, Braunschweig, Germany)
Roemer, Friedhard; Witzigmann, Bernd (Computational Electronics and Photonics (CEP), Universität Kassel, Kassel, Germany)

Inhalt:
A top-down fabrication approach of GaN vertical transistors through integrating vertically aligned nanowires (NWs) has been reported here. By employing wet chemical etching, NWs with smooth a-plane sidewalls as well as special mushroom-like geometry are realized. The diameter of NWs can be controlled to be as small as 50 nm and their aspect ratio can reach up to 60. A fabricated transistor, integrating 99 NWs, exhibits enhancement-mode (E-mode) operation with a threshold voltage of 1.5 V, a high on and off current ratio of 109, a small subthreshold swing of 67 mV/Dec, and a high drain current (Id) output of Id > 10 mA, indicating that such vertical GaN devices are promising for future candidate in power electronics.