Predictive System-Level Constraint Verification and Optimization

Konferenz: Zuverlässigkeit und Entwurf - 9. ITG/GMM/GI-Fachtagung
18.09.2017 - 20.09.2017 in Cottbus, Deutschland

Tagungsband: Zuverlässigkeit und Entwurf

Seiten: 6Sprache: EnglischTyp: PDF

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Autoren:
Krinke, Andreas; Lei, Lei; Lienig, Jens (Dresden University of Technology, Institute of Electromechanical and Electronic Design (IFTE), Dresden, Germany)

Inhalt:
Further automation of analog and mixed-signal integrated circuit design requires the consistent consideration of a growing number of design constraints through all design stages. However, the verification of system-level constraints is only possible towards the end of the design process when all necessary parameters are known. In this paper, we present a method for constraint state prediction in the early stages of an analog IC design project. This allows constraint consideration already during system-level design. By modeling yet unknown design parameters as random variables, the probability of a constraint to be fulfilled can be estimated. Constraint sensitivity analysis is used to identify design parameters with the most influence on a constraint’s state. Finally, design parameters are optimized to maximize the probability of fulfilling all constraints.