Investigations of Annealing Effect on TSV CMP
Konferenz: ICPT 2017 - International Conference on Planarization/CMP Technology
11.10.2017 - 13.10.2017 in Leuven, Belgium
Tagungsband: ICPT 2017
Seiten: 4Sprache: EnglischTyp: PDF
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Autoren:
Rao, Can; Wang, Tongqing; Cheng, Jie; Liu, Yuhong; Lu, Xinchun (State key lab of tribology, Tsinghua University, Beijing 100084, China)
Inhalt:
For Through-silicon via wafer, the quality after chemical-mechanical planarization is of great importance to 3D IC integration. The wafer profile, non-uniformity, and dishing result are the key parameters. Meanwhile, the annealing process before CMP has impact on CMP performance. In this paper we conduct TSV CMP experiments with different annealing conditions. Key parameters under consideration include annealing time and temperature. Keywords: Through-silicon Via, Chemical-mechanical Planarization, Annealing, Via dishing, Non-uniformity