CMP Process for Wafer Backside Planarization

Konferenz: ICPT 2017 - International Conference on Planarization/CMP Technology
11.10.2017 - 13.10.2017 in Leuven, Belgium

Tagungsband: ICPT 2017

Seiten: 5Sprache: EnglischTyp: PDF

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Autoren:
Krueger, Andreas; Lisker, Marco; Trusch, Andreas; Mai, Andreas (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany)

Inhalt:
In this work we present a wafer backside planarization process. This process is used to reduce the wafer backside surface roughness on a fully processed BiCMOS wafer to enable suitable surface conditions for the bonding processes (permanent or temporary) from wafer to wafer. Such process is required to remove material stacks from the wafer backside which were deposited during front end of line furnace processes (like SiO2 and SiN low pressure chemical vapor deposition (LPCVD) and Silicon-Germanium epitaxy). The surface roughness of the wafer backside after CMP is reduced from 170 nm Rq down to <0.3 nm Rq (root-mean-squared roughness). Applications for wafer the backside CMP are for example: First, surface preparation for wafer-to-wafer bonding-A certain roughness of the wafer surface is required on the wafer backside to enable infrared light transmission through the wafer to realize a sufficient alignment of the wafers. Secondly the backside planarization is required to remove the surface roughness for the following photolithography process steps. Moreover, this backside CMP process is also capable to remove the roughness after a wafer grinding process. Keywords: Planarization, Chemical-mechanical Polishing, ICPT 2017, Wafer Backside, Surface Roughness, Wafer Bonding