Benchmark of the gate driver supplies' architectures for "N" power devices in series connection

Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland

Tagungsband: ETG-Fb. 156: CIPS 2018

Seiten: 6Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Autoren:
Nguyen, Van-Sang; Lefranc, Pierre; Crebier, Jean-Christophe (Univ. Grenoble Alpes, CNRS, Grenoble INP, G2ELab, 38000 Grenoble, France)

Inhalt:
This paper presents a design benchmark in order to optirnize the gate driver circuitries that need to be implemented to drive power devices in series connection. More precisely, the impacts of the gate driver supplies circuitries over the conducted EMI perturbations in common mode from the power parts to the gate driver circuitry, the switching speeds of the power devices themselves, the power rating, the galvanic isolation ratings of the gate driver's power supplies and the power consumption ofthe gate driver circuit are taken into account. Based on previous works on the conducted EMI perturbations and the analysis of the switching speed of two power devices in series connection, this paper analyses, from a theoretical point of view, for several representative gate driver supplies architectures the efficiency of the supplies of the gate drivers, the volume, and the perturbations on each power supply. This analysis is carried out from 2 to 6 power devices in series connection and is finally generalized to "N" power devices in series connection.