Solder layer degradation measurement for SiC-MOSFET Modules under accelerated power cycling conditions
Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland
Tagungsband: ETG-Fb. 156: CIPS 2018
Seiten: 5Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Luo, Haoze; Iannuzzo, Francesco; Blaabjerg, Frede (Aalborg University, Aalborg, Denmark)
Die-attach solder layer and bond wires are the two weakest parts in power modules. In order to distinguish the solder layer and bond wire degradation during accelerated tests, a simultaneous on-line measurement method is proposed in this paper. By means of auxiliary source terminal, both the solder layer resistance increase and bond wire resistance increase can be measured and monitored separately. To measure accurately the solder layer degradation, the intrinsic diode is used as heating source in place of the MOSFET switch. In this way, the measurement method becomes intrinsically insensitive to possible threshold voltage shifts, typical of accelerated tests of SiC power MOSFETs. Finally, the experimental results are presented to verify the feasibility of the proposed test method. It is revealed that the solder layer resistance increases linearly with the number of cycles in good approximation.