Double chips low side - high side configurable full gate driver circuits for high speed inverter leg

Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland

Tagungsband: ETG-Fb. 156: CIPS 2018

Seiten: 6Sprache: EnglischTyp: PDF

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Crebier, Jean-Christophe; Nguyen, Van-Sang; Lefranc, Pierre (Univ. Grenoble Alpes, CNRS, Grenoble INP, G2ELab, 38000 Grenoble, France)
Rouger, Nicolas (Univ. Toulouse, LAPLACE, CNRS, INPT, UPS, 31071 Toulouse, France)
Grezaud, Romain; Ayel, Francois (Univ. Grenoble Alpes, CEA LETI, MINATEC Campus, 38000 Grenoble, France)
Saboret, Xavier; Latimier, Paul-Emile (SERMA IDMOS, 33600 Pessac, France)

The paper presents the work carried out to develop, prototype and characterize a gate driver circuitry for inverter legs, all integrated in two ASICs, one for the low side power device and the second to drive the high side device. The proposed configuration integrates, all in one, low side - high side gate driver supplies, bidirectional communication interface as well as several original functionalities. The gate drivers’ circuitry is based on a cascaded architecture that prevent from EMI propagations. Especially, the driver circuitry includes on-board digital functionalities such as PWM generation, dead time management, auto skew and configurable switching transition delays for optimal voltage inverter leg switching transitions. The whole driver circuitry can be configured and operated in real time mode thanks to an isolated I2C communication interface. The paper presents the architecture, details the characteristics of some functionalities and provides preliminary results related to low side - high side bidirectional communication.