Towards Wafer Level 3D Power Integration

Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland

Tagungsband: ETG-Fb. 156: CIPS 2018

Seiten: 5Sprache: EnglischTyp: PDF

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Autoren:
Charbonnier, Jean; Rat, Venceslass; Carvalho, Hamilton de; Bergogne, Dominique (Univ. Grenoble Alpes, 38000 Grenoble France & CEA, LETI, MINATEC Campus, 38054 Grenoble France)
Siegert, Joerg (AMS AG, 8141 Premstaetten, Austria)
Pressel, Klaus (Infineon Technologies AG, 93049 Regensburg, Germany)

Inhalt:
Wafer level 3D technologies provide an interesting path towards integrated power systems. In the framework of the ENIAC JU project Enhanced Power Pilot Line (EPPL), a new type of device has been studied, integrating lateral power devices onto a silicon interposer. This paper presents an experimental H bridge of four lateral power MOS transistors assembled onto a Through Silicon Via (TSV) Passive Silicon Interposer and tested within an application board.