Novel SiC Module Design – Optimised for Low Switching Losses, Efficient Cooling Path and Low Inductance
Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland
Tagungsband: ETG-Fb. 156: CIPS 2018
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Huber, Thomas; Kleimaier, Alexander (University of Applied Sciences Landshut, Landshut, Germany)
Applying a novel two-layer module design, a low inductive 600V / 200A SiC module with integrated DC-link and EMI shielding layer was designed. The power loop inductance of 1.6 nH is noticeable lower than known from conventional power module setups. The low inductive design allows for very fast switching with low over-voltage and minimum oscillations. Compared to a reference module without any external gate resistance, the switching losses can be lowered by 22.5 %. Compared to the same module with RG(ext) = 2.3 Ω nearly datasheet value and therefore with a smooth, but slower switching behaviour of the reference, the reduction amounts 80 %. The novel design needs only 43% of the chip area, which was applied in the reference module. – To ensure an appropriate die cooling with the new two-layer structure, different cooling concepts are presented. Applying three-dimensional static thermal models for each concept, the junction temperature of power semiconductors is evaluated and the thermal resistance is calculated. A promising stacked ceramic substrate design provides a slightly higher thermal resistance value with respect to conventional one-layer power modules.