Benefits of new CoolSiCTM MOSFET in HybridPACKTM Drive package for electrical drive train applications.

Konferenz: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
20.03.2018 - 22.03.2018 in Stuttgart, Deutschland

Tagungsband: ETG-Fb. 156: CIPS 2018

Seiten: 9Sprache: EnglischTyp: PDF

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Autoren:
Jakobi, Waldemar; Uhlemann, Andre; Thoben, Markus (Infineon Technologies AG, Max-Planck-Str. 5, 59581 Warstein, Germany)
Schweikert, Christian; Strenger, Christian; Pai, Ajay Poonjal; Beaurenaut, Laurent; Muenzer, Mark (Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany)

Inhalt:
For hybrid and electric vehicles it is necessary to increase the power density in order to keep the system compact and to expand the power range of the car. There are different options to increase the power density like better chips with wide band gap materials, an improved cooling system or an innovative interconnection- and joining technology for elevated operation temperatures. In this paper Infineon’s new 1200V CoolSiC(Exp TM) MOSFET is presented, integrated and tested in the upcoming HybridPACK (Exp TM) Drive power module. The power module is designed for high power main inverter applications up to 300kW and for switching currents up to 500A RMS. For this application several SiC-MOSETS devices must be arranged and controlled in parallel connection. For this reason a new low inductive DCB/AMB layout concept is developed. Different investigations (experimental and simulative ones) were performed to reduce current fail distribution to a minimum. These considerations are also interesting from a reliability point of view, because current fail distribution could limit the life time expectation. Furthermore the switching behavior of SiC MOSFET is discussed especially with focus on overvoltage and oscillations effects which can be critical for inverter operations. Influence of e.g. RC snubber solutions and operation modes will be also discussed in this paper. In addition to these aspects, the switching losses will be compared with state of the art chip technologies to figure out the increase of efficiency in dependence on the considered working points.