A reusable Triple Core 12-bit Current Steering Digital-to-Analog Converter for high performance Transceivers in lndustry 4.0 Applications

Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland

Tagungsband: GMM-Fb. 91: ANALOG 2018

Seiten: 6Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Autoren:
Wittmann, Reimund; Steinkamp, Jan; Henkel, Frank (IMST GmbH, Carl-Friedrich-Gauß-Str. 2, 47475 Kamp-Lintfort, Germany)
Tittelbach-Helmrich, Klaus (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany)
Wolf, Andreas (Dr. WolfWireless GmbH, Paul-Gerhardt-Str. 9, 14513 Teltow, Germany)

Inhalt:
This work presents a novel 12-bit 60 MHz triple core concept for a current-steering CMOS digital-to-analog converter (DAC) for use in high performance wireless transmitter circuits. The main core focuses on the 12 bit baseband signal conversion with a sampling rate of 60 MHz. An assisting second core forms a configurable attenuator circuit, which allows gain adjustments down to 0.025 % FSR (linear) or down to 0.25 dB (logarithmic) steps. The implemented multiplying architecture utilizes dynamic LSB current scaling, which remarkably improves the signal-to-noise performance for attenuated baseband signals. A third core enables real time linearization during full speed operation. The linearity performance oft he main core depends on the matching characteristics of the segmented current source arrays. The presented correction technique is able to decouple the traditional trade-off between area requirements and achievable linearity performance. The implemented additive approach is designed to introduce corrections of up to 4 LSB with a step size of 0.5 LSB for any point of the DAC 4096-step transfer function. The presented architecture is configurable for a wide set of applications. For the targeted Industry 4.0 radio system an oversampling ratio of 3 is applied. The main core is organized into an 8-3-1 segmented structure, which minimizes area for the specified dynamic performance. The basic current cell has been optimized for low glitch operation. The full circuit operates with a single 1.5 V supply and the total power consumption is 35 mW. SINAD value stays close to 70 dB for attenuator settings from 0 to 12 dB. The worst case glitch energy is less than 2.8 pVs. The active area of the fully differential DAC with three cores is 0.25 mm2 in a 130 nm standard CMOS technology.