Modeling of Δ-Σ Modulators for Low-Power Audio Applications

Inhalt:
This paper presents an architecture study of higher order δ-σ modulators to be used in audio applications where medium performance at very low power consumption is required such as hearing aids. A comparison between third and fourth order modulators is done based on a tradeoff between achievable resolution and noise floor versus power consumption. A python ported package of Richard Schreier’s Δ-Σ Toolbox[1] was used for the initial analysis followed by corresponding implementation in Simulink. The various circuit level non-idealities were introduced based on approximate values obtained from Cadence simulations run for a 22 nm CMOS FDSOI process, which led to finalizing the minimal OTA performance parameters to 40 dB DC gain and 10 MHz unity GBW (modulator clock frequency = 2.5 MHz). The modulator post decimation and filtering achieves an SNDR of 102.7 dB (Target SNDR = 90dB) and a THD of -134.3 dB, thus providing a margin for process variations and DAC noise floor.