Modeling of Δ-Σ Modulators for Low-Power Audio Applications
Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland
Tagungsband: GMM-Fb. 91: ANALOG 2018
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Barretto, Ciana; Herzer, Elmar; Agashe, Akshay; Hauer, Johann (Fraunhofer IIS, Erlangen, Germany)
Meiners, Mirco (Hochschule Bremen-City University of Applied Sciences, Bremen, Germany)
This paper presents an architecture study of higher order δ-σ modulators to be used in audio applications where medium performance at very low power consumption is required such as hearing aids. A comparison between third and fourth order modulators is done based on a tradeoff between achievable resolution and noise floor versus power consumption. A python ported package of Richard Schreier’s Δ-Σ Toolbox was used for the initial analysis followed by corresponding implementation in Simulink. The various circuit level non-idealities were introduced based on approximate values obtained from Cadence simulations run for a 22 nm CMOS FDSOI process, which led to finalizing the minimal OTA performance parameters to 40 dB DC gain and 10 MHz unity GBW (modulator clock frequency = 2.5 MHz). The modulator post decimation and filtering achieves an SNDR of 102.7 dB (Target SNDR = 90dB) and a THD of -134.3 dB, thus providing a margin for process variations and DAC noise floor.