Analysis and optimization of voltage reference circuits based on sub-1V MOSFETs operating in different CMOS technologies
Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland
Tagungsband: GMM-Fb. 91: ANALOG 2018
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Quarata, Giuseppe (University of Salerno, Italy)
Pronath, Michael (MunEDA GmbH, München, Germany)
This paper presents the design and implementation of a precision voltage reference circuit using MOSFETs operating in the subthreshold region. Four different types of voltage reference circuits are investigated. We simulate and optimize them in 0.18-µm and 28-nm CMOS technology and compare the new values obtained with the original ones. For 28-nm technology, the circuits provide a different reference voltage depending on the different type of simulation and functional constraints defined on each device. Circuit optimization software is used to satisfy all the constraints. We also show the effect of technological downsizing in the design of voltage reference circuits. The supply voltage is 1.8V for 0.18-µm CMOS technology with ±20% accuracy. Different results are obtained with optimal TC values around 20.33 ppm/°C in a temperature range of -20 to 120 °C. The supply voltage is 0.9V for 28-nm CMOS technology with ±20% accuracy. Different results are obtained with optimal TC values around 31.27 ppm/°C in a temperature range of -20 to 120 °C. Conversely Line Sensitivity (LS) gets worse considerably with values around 3.1 %/V due to the non-ideal effect of ultrascaling.