Considerations on the Design Methodology for an Integrated Gate Driver

Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland

Tagungsband: GMM-Fb. 91: ANALOG 2018

Seiten: 5Sprache: EnglischTyp: PDF

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Fiebig, Norbert; Fischer, Gunter; Ostrovskyy, Pylyp (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany)
Kissinger, Dietmar (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany & Technische Universität Berlin, Einsteinufer 17, 10587 Berlin, Germany)

Design considerations for a high-voltage output driver in a 0.13 µm 3.3 V BiCMOS technology are presented. The use of a stacked devices topology allows the driver to operate at three times the nominal supply voltage. Hot carrier degradation is reduced by operating within the voltage limits forced by the design rules. A design with only fully isolated transistors realizes negative supply domains which deliver a swing of -7.5 V with a peak current of 2.8 A at the switched output stage. Experiences during the different design phases are provided. Hints for using soft- and hardware, for the measurement and for the macro modelling are indicated.