On Applying Pareto Optimization for Complete Performance Space Modeling of Analog ICs
Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland
Tagungsband: GMM-Fb. 91: ANALOG 2018
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Schreiber, David; Kampe, Juergen (Ernst-Abbe-Hochschule, University of Applied Sciences Jena, Germany)
This paper is about performance space exploration for analog circuits by means of Pareto optimization. The aim of the proposed scheme is to generate evenly spread points on its enclosing surfaces, based on spice-simulation results. Advanced methods are applied for a successive approximation of all possible trade-offs. The Normal Boundary Intersection method is used not only for optimal trade-off points, but also to explore the opposite and adjoining boundaries. As a result, we get points on the boundary of the complete feasible performance space. The method described, is shown on a two stage transconductance amplifier in CMOS technology, with two different topology improvements. Three competing performance parameters are taken into account. Advantages of such performance space models could be graphical topology or technology comparison and high level modeling of transistor level circuits.