Automatic Analog-on-Top Chip-Level Schematic Generation Based on Wire-by-Name Methodology Juergen Wittmann, Carsten Wegener,
Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland
Tagungsband: GMM-Fb. 91: ANALOG 2018
Seiten: 5Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Wittmann, Juergen; Wegener, Carsten; Rigoni, Fabio (Dialog Semiconductor, Germering, Germany)
The standard form of analog design is “drawing” a schematic. Applying this to a chip-level with more than 100 IP instantiations, 5000 digital and 500 analog signals becomes a tedious and error-prone task. To improve efficiency and manage chip-level complexity, the schematic generation is approached differently. An Excel database contains all chip-level related design information, required for the IC development. A list of IP instantiations referencing to a sub-circuit cell is defined in the database. The chip-level schematic is generated by an automatic schematic generator based on a wire-by-name approach according to predefined wire name conventions. The connectivity of each top-level instantiation of a cell is obtained from the cell pin names and the instance name. Instances are connected by resulting wire names. The Excel database enables to consistently maintaining design information for chip layout, digital design, verification, and others development disciplines in one single database, and achieves a high level of alignment within a project, and even across projects, when circuit blocks are re-used.