Parallelization Strategies for the Detailed Routing Step
Konferenz: ANALOG 2018 - 16. GMM/ITG-Fachtagung
13.09.2018 - 14.09.2018 in München/Neubiberg, Deutschland
Tagungsband: GMM-Fb. 91: ANALOG 2018
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Bredthauer, Bjoern; Olbrich, Markus; Barke, Erich (Institute of Microelectronic Systems, Leibniz Universität Hannover, Hannover, Germany)
Since processor speeds have plateaued in recent years, other avenues need to be explored to speed up Electronic Design Automation (EDA) applications in order to keep pace with the growing complexity of VLSI designs. The ubiquity of multicore processors makes parallelization an obvious approach for achieving further performance improvements. However, fully realizing the potential provided by many-core systems requires the algorithms to be carefully designed to avoid bottlenecks. The detailed routing step can take a lot of time and therefore is a good candidate for performance improvements. However, the necessity of generating legal routing results makes it challenging to scale to lots of processing cores due to the necessary communication overhead. This paper gives an overview on different approaches to the problem. Furthermore, we identify the core problems of different approaches.