Innovative Design Methodology for Analog-to-Digital and Digital-to-Analog Converters

Konferenz: ANALOG 2020 - 17. ITG/GMM-Fachtagung
28.09.2020 - 30.09.2020 in online

Tagungsband: ITG-Fb. 293 Analog 2020

Seiten: 6Sprache: EnglischTyp: PDF

Wittmann, Reimund; Henkel, Frank (IMST GmbH, Kamp-Lintfort, Germany)
Ripp, Andreas (MunEDA GmbH, Unterhaching, Germany)
Meyer, Alexander; Wunderlich, Ralf; Heinen, Stefan (RWTH Aachen University, Germany)
Dietrich, Manfred (Dikuli, Müllrose, Germany)

In modern signal processing systems, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) serve as a bridge between the real, analog world and digital information processing. As the demands on these converters are constantly increasing, the traditional, mostly manual design process becomes the determining time factor in circuit development. The BMBF project MeKoWA is therefore investigating new approaches in automating the design of these key elements in order to effectively counteract the impending bottleneck for integrated applications such as the Internet of Things, for driving assistance or for industrial automation (Industry 4.0). In a first step, ADC and DAC topologies were evaluated in terms of their flexibility and reliability towards meeting the demands of the industry. Special care was taken to ensure that both, transceiver applications for radio interfaces and sensor/actuator applications can be covered. A technology- and application-decoupled intellectual property (IP) library is currently implemented. The Σ-Δ (SD), pipeline and successive-approximation-register (SAR) concepts were chosen as ADC topologies. Consequently, the same analyses were performed for DAC topologies, leading to current-steering and potentiometer DACs being identified as suitable concepts. An efficient and automated design procedure supporting the targeted IP library concept is presented. It is based on the Cadence Virtuoso Design Framework and MunEDA’s WiCkeD and Schematic Porting Tool (SPT). First demonstrators of technology- and application decoupled data converter IPs are under development and first siliconverified results are presented in this work.