An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Martins, Ricardo; Canelas, Antonio; Lourenco, Nuno (Instituto de Telecomunicações, Lisboa, Portugal)
Gusmao, Antonio; Horta, Nuno (Instituto de Telecomunicações, Lisboa, Portugal & Instituto Superior Técnico, Universidade de Lisboa, Portugal)
Passos, Fabio (Instituto de Telecomunicações, Lisboa, Portugal & Dialog Semiconductors, Lisboa, Portugal)

Despite the fact that analog and radio-frequency (A/RF) integrated circuit (IC) design automation has been intensively studied in the last few decades, only automatic circuit-level sizing methodologies have achieved a satisfactory level of maturity. Layout and its countless issues have challenged all automation attempts, and two limiting factors must be addressed to force their way into the industrial environment: plug-and-play capabilities and accurate assessment of post-layout performance degradation. This paper brainstorms around the idea of developing the ultimate fully automatic “performance-driven” A/RF IC synthesis by incorporating simulation-based layout optimization concepts in the flow. The essay is carried the PONDEROUS tool, a novel and highly integrated, but exceptionally computationally intensive, placement A/RF IC optimizer.