RTL Implementation of MCMC-based Constraints Solver

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Ahmed, Moemen; Ahmed, Youssef; Nagy, Younan; Adbel-Rahman, Manar; El-Kharashi, M. Watheq (Department of Computer and Systems, Faculty of Engineering, Ain Shams University, Cairo, Egypt)
Salah, Khaled; Khan, Ayub (Siemens Digital Industries Software, Fremont, USA)

Functional hardware verification is one of the most challenging areas in the hardware design cycle. With the increase in the complexity and size of the design, the time needed for verification becomes the largest part of the total design time. The most recent technique in practical verification is constrained random simulation. This method needs a solver to produce random input stimuli that satisfies a pre-defined set of input constraints. The efficiency of the overall verification process depends critically on the speed of the constraints solver and the distribution of the generated solutions. In this paper, we propose hardware acceleration for RTL constraints solver integrated with SystemVerilog. The solver is based on Markov Chains Monte Carlo methods.