Extending a RISC-V core with an AES hardware accelerator to meet IOT constraints
Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online
Tagungsband: SMACD / PRIME 2021
Seiten: 4Sprache: EnglischTyp: PDF
Zgheib, Anthony; Potin, Olivier; Rigaud, Jean-Baptiste; Dutertre, Jean-Max (Mines Saint-Etienne, CEA-Tech Centre CMP, Gardanne, France)
Internet of Things devices and applications are subject to strong constraints in terms of cost, code size and power consumption. This leads to difficulties in using resourcehungry encryption algorithms to ensure the confidentiality of the exchanged data. In this paper, we extend with a custom instruction the RISC-V open source Instruction Set Architecture (ISA) and integrate an Advanced Encryption Standard (AES) hardware accelerator to an IBEX RISC-V core. This is achieved for the sake of reducing its energy consumption, encryption time and code size with respect to purely AES software solutions. We consider a Field Programmable Gate Array implementation and ascertain its relevance for an Electrocardiography use case.