A 12-bit 100 MHz SAR ADC in 110-nm CMOS for MAPSs
Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online
Tagungsband: SMACD / PRIME 2021
Seiten: 4Sprache: EnglischTyp: PDF
Tedesco, Silvia (Department of Electrical, Electronics and Communications Engineering, Politecnico di Torino, Italian Institute of Nuclear Physics - Sezione di Torino, Turin, Italy)
This paper presents a fully differential 12-bit SAR ADC developed for high-voltage CMOS sensors. The converter has been designed in compliance with low power consumption, high resolution and low material budget requirements. A merged capacitor switching method is employed to decrease power consumption and the capacitor array has been split up into two sub-DACs in order to reduce the area. The prototype has been implemented in a 110-nm CMOS technology. With a power supply of 1.2 V and a 100 MHz clock, simulations show an ENOB 9.87 of and a SFDR of 73.42 dB. The power consumption of the ADC is 513 muW while the Figure of Merit (FOM) results 54.8 fJ/conv-step. The final chip includes also a calibration engine to minimize the capacitor mismatch effect thus further improving the resolution.