A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Ricci, Luca; Bertulessi, Luca; Bonfanti, Andrea (Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Milan, Italy)

This paper presents a high-speed and low-noise comparator implemented in a 28-nm bulk CMOS technology with a 0.9-V supply voltage. The comparator is designed for a 12- bit 200-MSps successive-approximation-register (SAR) analogto- digital converter (ADC). Simulations show an input-referred noise of 163 muV and a reset-out delay of 110-ps for an input differential voltage of 100 muV. The energy per conversion is 595 fJ/conv and the Figure-of-Merit is 15.8 nJmuV2, better than the state of the art.